On Thu, 10 Dec 2020 15:58:02 +0530, Yash Shah wrote: > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > compared to 3 in FU540. Update the DT documentation accordingly with > "compatible" and "interrupt" property changes. > > Signed-off-by: Yash Shah <yash.s...@sifive.com> > --- > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 > +++++++++++++++++++--- > 1 file changed, 30 insertions(+), 4 deletions(-) >
Reviewed-by: Rob Herring <r...@kernel.org>