> -----Original Message-----
> From: Bin Meng <[email protected]>
> Sent: 10 December 2020 19:05
> To: Yash Shah <[email protected]>
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected]; linux-kernel <linux-
> [email protected]>; linux-riscv <[email protected]>;
> devicetree <[email protected]>; open list:GPIO SUBSYSTEM <linux-
> [email protected]>; [email protected]; Greg Kroah-Hartman
> <[email protected]>; Albert Ou <[email protected]>;
> [email protected]; [email protected]; Thierry Reding
> <[email protected]>; [email protected]; Peter Korsgaard
> <[email protected]>; Paul Walmsley ( Sifive)
> <[email protected]>; Palmer Dabbelt <[email protected]>; Rob
> Herring <[email protected]>; Bartosz Golaszewski
> <[email protected]>; Linus Walleij <[email protected]>
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive
> FU740-
> C000 SoC
>
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>
> On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <[email protected]> wrote:
> >
> > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
>
> FU740-C000 Soc
>
> > around the SiFIve U7 Core Complex and a TileLink interconnect.
> >
> > This file is expected to grow as more device drivers are added to the
> > kernel.
> >
> > Signed-off-by: Yash Shah <[email protected]>
> > ---
> > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > +++++++++++++++++++++++++++++
> > 1 file changed, 293 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > new file mode 100644
> > index 0000000..eeb4f8c3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > @@ -0,0 +1,293 @@
...
> > + plic0: interrupt-controller@c000000 {
> > + #interrupt-cells = <1>;
> > + #address-cells = <0>;
> > + compatible = "sifive,fu540-c000-plic",
> > + "sifive,plic-1.0.0";
>
> I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
That's because it is not required. There won't be any difference in driver code
for FU740 plic.
...
> > + eth0: ethernet@10090000 {
> > + compatible = "sifive,fu540-c000-gem";
>
> "sifive,fu740-c000-gem"?
>
Same reason as above.
Thanks for your review.
- Yash
> > + interrupt-parent = <&plic0>;
> > + interrupts = <55>;
> > + reg = <0x0 0x10090000 0x0 0x2000>,
> > + <0x0 0x100a0000 0x0 0x1000>;
> > + local-mac-address = [00 00 00 00 00 00];
> > + clock-names = "pclk", "hclk";
> > + clocks = <&prci PRCI_CLK_GEMGXLPLL>,
> > + <&prci PRCI_CLK_GEMGXLPLL>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > + };
> > + pwm0: pwm@10020000 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x10020000 0x0 0x1000>;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <44>, <45>, <46>, <47>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + pwm1: pwm@10021000 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x10021000 0x0 0x1000>;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <48>, <49>, <50>, <51>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + ccache: cache-controller@2010000 {
> > + compatible = "sifive,fu740-c000-ccache", "cache";
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <2048>;
> > + cache-size = <2097152>;
> > + cache-unified;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <19 20 21 22>;
> > + reg = <0x0 0x2010000 0x0 0x1000>;
> > + };
> > + gpio: gpio@10060000 {
> > + compatible = "sifive,fu740-c000-gpio",
> > "sifive,gpio0";
> > + interrupt-parent = <&plic0>;
> > + interrupts = <23>, <24>, <25>, <26>, <27>, <28>,
> > <29>,
> > + <30>, <31>, <32>, <33>, <34>, <35>,
> > <36>,
> > + <37>, <38>;
> > + reg = <0x0 0x10060000 0x0 0x1000>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + status = "disabled";
> > + };
> > + };
> > +};
>
> Regards,
> Bin
