> -----Original Message-----
> From: Bin Meng <[email protected]>
> Sent: 16 December 2020 11:36
> To: Yash Shah <[email protected]>
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected]; linux-kernel <linux-
> [email protected]>; linux-riscv <[email protected]>;
> devicetree <[email protected]>; open list:GPIO SUBSYSTEM <linux-
> [email protected]>; [email protected]; Greg Kroah-Hartman
> <[email protected]>; Albert Ou <[email protected]>;
> [email protected]; [email protected]; Thierry Reding
> <[email protected]>; [email protected]; Peter Korsgaard
> <[email protected]>; Paul Walmsley ( Sifive)
> <[email protected]>; Palmer Dabbelt <[email protected]>; Rob
> Herring <[email protected]>; Bartosz Golaszewski
> <[email protected]>; Linus Walleij <[email protected]>
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive
> FU740-
> C000 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> Hi Yash,
>
> On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <[email protected]>
> wrote:
> >
> > > -----Original Message-----
> > > From: Bin Meng <[email protected]>
> > > Sent: 10 December 2020 19:05
> > > To: Yash Shah <[email protected]>
> > > Cc: [email protected]; [email protected]; linux-
> > > [email protected]; [email protected]; linux-kernel <linux-
> > > [email protected]>; linux-riscv
> > > <[email protected]>;
> > > devicetree <[email protected]>; open list:GPIO SUBSYSTEM
> > > <linux- [email protected]>; [email protected]; Greg
> > > Kroah-Hartman <[email protected]>; Albert Ou
> > > <[email protected]>; [email protected];
> > > [email protected]; Thierry Reding
> > > <[email protected]>; [email protected]; Peter Korsgaard
> > > <[email protected]>; Paul Walmsley ( Sifive)
> > > <[email protected]>; Palmer Dabbelt <[email protected]>;
> Rob
> > > Herring <[email protected]>; Bartosz Golaszewski
> > > <[email protected]>; Linus Walleij
> > > <[email protected]>
> > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the
> > > SiFive FU740-
> > > C000 SoC
> > >
> > > [External Email] Do not click links or attachments unless you
> > > recognize the sender and know the content is safe
> > >
> > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <[email protected]>
> wrote:
> > > >
> > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is
> > > > built
> > >
> > > FU740-C000 Soc
> > >
> > > > around the SiFIve U7 Core Complex and a TileLink interconnect.
> > > >
> > > > This file is expected to grow as more device drivers are added to
> > > > the kernel.
> > > >
> > > > Signed-off-by: Yash Shah <[email protected]>
> > > > ---
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > > > +++++++++++++++++++++++++++++
> > > > 1 file changed, 293 insertions(+) create mode 100644
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > new file mode 100644
> > > > index 0000000..eeb4f8c3
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > @@ -0,0 +1,293 @@
> >
> > ...
> >
> > > > + plic0: interrupt-controller@c000000 {
> > > > + #interrupt-cells = <1>;
> > > > + #address-cells = <0>;
> > > > + compatible = "sifive,fu540-c000-plic",
> > > > + "sifive,plic-1.0.0";
> > >
> > > I don't see bindings updated for FU740 PLIC, like
> > > "sifive,fu740-c000-plic"?
> >
> > That's because it is not required. There won't be any difference in driver
> code for FU740 plic.
>
> Are there any driver changes for the drivers that have an updated
> fu640-c000-* bindings? I don't see them in the linux-riscv list.
Yes, they will be posted soon.
- Yash
>
> >
> > ...
> >
> > > > + eth0: ethernet@10090000 {
> > > > + compatible = "sifive,fu540-c000-gem";
> > >
> > > "sifive,fu740-c000-gem"?
> > >
> >
> > Same reason as above.
> >
> > Thanks for your review.
>
> Regards,
> Bin
