[PATCH 1/3] arm64: dts: qcom: sm8150: Define CPU topology

[Danny Lin]

sm8150 has a big.LITTLE CPU setup with DynamIQ, so all cores are within
the same CPU cluster and LLC (Last-Level Cache) domain. Define this
topology to help the scheduler make decisions.

Signed-off-by: Danny Lin <da...@kdrag0n.dev>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 36 ++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi 
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index b58cf1b8542c..75ed38ee5d88 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -160,6 +160,42 @@ L2_700: l2-cache {
                                next-level-cache = <&L3_0>;
                        };
                };
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&CPU0>;
+                               };
+
+                               core1 {
+                                       cpu = <&CPU1>;
+                               };
+
+                               core2 {
+                                       cpu = <&CPU2>;
+                               };
+
+                               core3 {
+                                       cpu = <&CPU3>;
+                               };
+
+                               core4 {
+                                       cpu = <&CPU4>;
+                               };
+
+                               core5 {
+                                       cpu = <&CPU5>;
+                               };
+
+                               core6 {
+                                       cpu = <&CPU6>;
+                               };
+
+                               core7 {
+                                       cpu = <&CPU7>;
+                               };
+                       };
+               };
        };
 
        firmware {
-- 
2.29.2