[PATCH v3 09/17] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled

[Like Xu]

The bit 12 represents "Processor Event Based Sampling Unavailable (RO)" :
        1 = PEBS is not supported.
        0 = PEBS is supported.

A write to this PEBS_UNAVL available bit will bring #GP(0) when guest PEBS
is enabled. Some PEBS drivers in guest may care about this bit.

Signed-off-by: Like Xu <like...@linux.intel.com>
---
 arch/x86/kvm/vmx/pmu_intel.c | 2 ++
 arch/x86/kvm/x86.c           | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index c04e12812797..99d9453e0176 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -426,6 +426,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
                INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters);
 
        if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) {
+               vcpu->arch.ia32_misc_enable_msr &= 
~MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
                if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_BASELINE) {
                        pmu->pebs_enable_mask = ~pmu->global_ctrl;
                        pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE;
@@ -436,6 +437,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
                } else
                        pmu->pebs_enable_mask = ~((1ull << 
pmu->nr_arch_gp_counters) - 1);
        } else {
+               vcpu->arch.ia32_misc_enable_msr |= 
MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
                vcpu->arch.perf_capabilities &= ~PERF_CAP_PEBS_MASK;
        }
 
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index a38ca932eec5..213368e47500 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -3095,6 +3095,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct 
msr_data *msr_info)
                break;
        case MSR_IA32_MISC_ENABLE:
                data &= ~MSR_IA32_MISC_ENABLE_EMON;
+               if (!msr_info->host_initiated &&
+                   (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) &&
+                   (data & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
+                       return 1;
                if (!kvm_check_has_quirk(vcpu->kvm, 
KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
                    ((vcpu->arch.ia32_misc_enable_msr ^ data) & 
MSR_IA32_MISC_ENABLE_MWAIT)) {
                        if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
-- 
2.29.2