On Wed 30 Dec 09:51 CST 2020, Iskren Chernev wrote:

> From: Brian Masney <masn...@onstation.org>
> 
> Add support for the a3xx GPU
> 
> Signed-off-by: Brian Masney <masn...@onstation.org>

As discussed on IRC I'm waiting for a respin of this with your S-o-b
added after Brian's.

Thanks,
Bjorn

> ---
>  arch/arm/boot/dts/qcom-msm8974.dtsi | 45 +++++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi 
> b/arch/arm/boot/dts/qcom-msm8974.dtsi
> index 51f5f904f9eb9..c399446d8154e 100644
> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
> @@ -1399,6 +1399,51 @@ cnoc: interconnect@fc480000 {
>                                <&rpmcc RPM_SMD_CNOC_A_CLK>;
>               };
>  
> +             gpu_opp_table: opp_table {
> +                     status = "disabled";
> +
> +                     compatible = "operating-points-v2";
> +
> +                     opp-800000000 {
> +                             opp-hz = /bits/ 64 <800000000>;
> +                     };
> +
> +                     opp-500000000 {
> +                             opp-hz = /bits/ 64 <500000000>;
> +                     };
> +
> +                     opp-275000000 {
> +                             opp-hz = /bits/ 64 <275000000>;
> +                     };
> +             };
> +
> +             gpu: adreno@fdb00000 {
> +                     status = "disabled";
> +
> +                     compatible = "qcom,adreno-330.2",
> +                                  "qcom,adreno";
> +                     reg = <0xfdb00000 0x10000>;
> +                     reg-names = "kgsl_3d0_reg_memory";
> +                     interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +                     interrupt-names = "kgsl_3d0_irq";
> +                     clock-names = "core",
> +                                   "iface",
> +                                   "mem_iface";
> +                     clocks = <&mmcc OXILI_GFX3D_CLK>,
> +                              <&mmcc OXILICX_AHB_CLK>,
> +                              <&mmcc OXILICX_AXI_CLK>;
> +                     sram = <&gmu_sram>;
> +                     power-domains = <&mmcc OXILICX_GDSC>;
> +                     operating-points-v2 = <&gpu_opp_table>;
> +
> +                     interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc 
> BIMC_SLV_EBI_CH0>,
> +                                     <&ocmemnoc OCMEM_VNOC_MAS_GFX3D 
> &ocmemnoc OCMEM_SLV_OCMEM>;
> +                     interconnect-names = "gfx-mem",
> +                                          "ocmem";
> +
> +                     // iommus = <&gpu_iommu 0>;
> +             };
> +
>               mdss: mdss@fd900000 {
>                       status = "disabled";
>  
> 
> base-commit: d7a03a44a5e93f39ece70ec75d25c6088caa0fdb
> prerequisite-patch-id: aba6f684932cab35d98457c21e4ff7a5ac75c753
> prerequisite-patch-id: 4884d57df1bd197896b69e115d9002d6c26ae2e2
> prerequisite-patch-id: 4f1aba3c3675236b18578eedbe71b0cdca01ed77
> prerequisite-patch-id: cbfe6ccfebb142370baff15bbdf3cf2f34ee77df
> -- 
> 2.29.2
> 

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