On Tue, Feb 2, 2021 at 1:18 PM Leizhen (ThunderTown)
<thunder.leiz...@huawei.com> wrote:
> On 2021/2/2 16:44, Arnd Bergmann wrote:
> >
> > To have a more useful performance number, try mentioning the
> > most performance sensitive non-coherent DMA master on one
> > of the chips that has this cache controller, and a high-level
> > performance number such as "1.2% more network packets per
> > second" if that is something you can measure easily.
>
> It's not easy. My board only have debugging NIC, only the downstream
> products have high-speed service NIC. Software needs to be packaged
> layer by layer.
>
> >
> > Of course, if all high-speed DMA masters on this chip are
> > cache coherent, there is no need for performance numbers, just
> > mention that we don't care about speed in that case.
>
> It's not cache coherent, otherwise, the L3 cache does not need to be
> operated.
Ok, I see. In this case, just explain that the high-speed NIC is not
cache-coherent, so this is expected to make a difference, even if you
can't quantify it exactly.
Arnd
