From: Grzegorz Jaszczyk <j...@semihalf.com>
Add "phys" entries pointing to COMPHYs to PCIe and USB3 nodes
Signed-off-by: Grzegorz Jaszczyk <j...@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kos...@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
index daffe136c523..bbd955909813 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
@@ -59,6 +59,8 @@
/* J9 */
&pcie0 {
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&comphy1 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
@@ -139,6 +141,9 @@
/* J7 */
&usb3 {
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&comphy0 0>;
+ phy-names = "usb";
};
/* J8 */
--
2.17.1
