Quoting Manivannan Sadhasivam (2021-01-17 20:11:51) > Changes in v2: > > * Modified the max_register value as per the SDX55 IPC offset in mailbox > driver. > > Manivannan Sadhasivam (5): > dt-bindings: mailbox: Add binding for SDX55 APCS > mailbox: qcom: Add support for SDX55 APCS IPC
I think I can apply the clk patches to clk tree without the mailbox patches, right? > dt-bindings: clock: Add Qualcomm A7 PLL binding > clk: qcom: Add A7 PLL support > clk: qcom: Add SDX55 APCS clock controller support >
