Hi Ikjoon,
Thank you for your patch.
Missatge de Ikjoon Jang <i...@chromium.org> del dia dc., 24 de febr.
2021 a les 10:21:
>
> mfgcfg clock is under MFG_ASYNC power domain
>
> Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
> Signed-off-by: Ikjoon Jang <i...@chromium.org>
> ---
>
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 5b782a4769e7..3384df5284c0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -962,6 +962,7 @@ mfgcfg: syscon@13000000 {
> compatible = "mediatek,mt8183-mfgcfg", "syscon";
> reg = <0 0x13000000 0 0x1000>;
> #clock-cells = <1>;
> + power-domains = <&scpsys
> MT8183_POWER_DOMAIN_MFG_ASYNC>;
I don't think this will work in mainline, at least, the reference name
should be &spm
Thanks,
Enric
> };
>
> mmsys: syscon@14000000 {
> --
> 2.30.0.617.g56c4b15f3c-goog
>
>
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