From: Richard Fitzgerald <[email protected]> The PLL is only needed for sclk < 11289600 Hz and cs42l42_pll_config() will not configure it for higher rates. So it must only be enabled when it is needed.
Signed-off-by: Richard Fitzgerald <[email protected]> --- sound/soc/codecs/cs42l42.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c index 5755f8baddbcf..68b5a450623d3 100644 --- a/sound/soc/codecs/cs42l42.c +++ b/sound/soc/codecs/cs42l42.c @@ -855,8 +855,9 @@ static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) } else { if (!cs42l42->stream_use) { /* SCLK must be running before codec unmute */ - snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, - CS42L42_PLL_START_MASK, 1); + if ((cs42l42->bclk < 11289600) && (cs42l42->sclk < 11289600)) + snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, + CS42L42_PLL_START_MASK, 1); /* Mark SCLK as present, turn off internal oscillator */ regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, -- 2.30.1
