Quoting Douglas Anderson (2021-03-15 10:38:54) > As per Dmitry Baryshkov [1]: > a) The 2nd "reg" should be 0x3c because "Offset 0x38 is > USB3_DP_COM_REVISION_ID3 (not used by the current driver though)."
I see 0x34 for the offset here instead of 0x38 but I don't think it really matters either way. > b) The 3rd "reg" "is a serdes region and qmp_v3_dp_serdes_tbl contains > registers 0x148 and 0x154." > > I think because the 3rd "reg" is a serdes region we should just use > the same size as the 1st "reg"? > > [1] https://lore.kernel.org/r/ee5695bb-a603-0dd5-7a7f-695e919b1...@linaro.org > > Cc: Stephen Boyd <swb...@chromium.org> > Cc: Jeykumar Sankaran <jsa...@codeaurora.org> > Cc: Chandan Uddaraju <chand...@codeaurora.org> > Cc: Vara Reddy <va...@codeaurora.org> > Cc: Tanmay Shah <tan...@codeaurora.org> > Cc: Rob Clark <robdcl...@chromium.org> > Fixes: 58fd7ae621e7 ("arm64: dts: qcom: sc7180: Update dts for DP phy inside > QMP phy") > Reported-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org> > Signed-off-by: Douglas Anderson <diand...@chromium.org> > --- Reviewed-by: Stephen Boyd <swb...@chromium.org>
