On 21-03-15 16:17:48, Richard Zhu wrote: > - The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock. > Change the sys2_pll_500m to sys2_pll_50m. > - Correct one mis-spell of the imx8mq_pcie1_ctrl_sels definition, from > "sys2_pll_250m" to "sys2_pll_333m". > > Signed-off-by: Richard Zhu <hongxing....@nxp.com>
Applied, thanks. > --- > drivers/clk/imx/clk-imx8mq.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > index 4dd4ae9d022b..c66c196f396c 100644 > --- a/drivers/clk/imx/clk-imx8mq.c > +++ b/drivers/clk/imx/clk-imx8mq.c > @@ -113,12 +113,12 @@ static const char * const imx8mq_disp_dtrc_sels[] = > {"osc_25m", "vpu_pll_out", " > static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", > "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", > "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", }; > > static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", > "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", > - "sys1_pll_800m", > "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", }; > + "sys1_pll_800m", > "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", }; > > static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", > "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2", > "clk_ext3", "clk_ext4", }; > > -static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", > "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out", > +static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", > "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out", > "sys2_pll_100m", "sys1_pll_80m", > "sys1_pll_160m", "sys1_pll_200m", }; > > static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", > "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", > "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", }; > -- > 2.17.1