Quoting Richard Zhu (2021-03-15 01:17:48) > - The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock. > Change the sys2_pll_500m to sys2_pll_50m. > - Correct one mis-spell of the imx8mq_pcie1_ctrl_sels definition, from > "sys2_pll_250m" to "sys2_pll_333m". > > Signed-off-by: Richard Zhu <hongxing....@nxp.com> > ---
Any Fixes tag?
