On Tue, Apr 13, 2021 at 11:37 AM Peter Zijlstra <pet...@infradead.org> wrote: > > On Tue, Apr 13, 2021 at 11:22:40AM +0200, Christoph Müllner wrote: > > > > For ticket locks you really only needs atomic_fetch_add() and > > > smp_store_release() and an architectural guarantees that the > > > atomic_fetch_add() has fwd progress under contention and that a sub-word > > > store (through smp_store_release()) will fail the SC. > > > > > > Then you can do something like: > > > > > > void lock(atomic_t *lock) > > > { > > > u32 val = atomic_fetch_add(1<<16, lock); /* SC, gives us RCsc */ > > > u16 ticket = val >> 16; > > > > > > for (;;) { > > > if (ticket == (u16)val) > > > break; > > > cpu_relax(); > > > val = atomic_read_acquire(lock); > > > } > > > } > > > > > > void unlock(atomic_t *lock) > > > { > > > u16 *ptr = (u16 *)lock + (!!__BIG_ENDIAN__); > > > u32 val = atomic_read(lock); > > > > > > smp_store_release(ptr, (u16)val + 1); > > > } > > > > > > That's _almost_ as simple as a test-and-set :-) It isn't quite optimal > > > on x86 for not being allowed to use a memop on unlock, since its being > > > forced into a load-store because of all the volatile, but whatever. > > > > What about trylock()? > > I.e. one could implement trylock() without a loop, by letting > > trylock() fail if the SC fails. > > That looks safe on first view, but nobody does this right now. > > Generic code has to use cmpxchg(), and then you get something like this: > > bool trylock(atomic_t *lock) > { > u32 old = atomic_read(lock); > > if ((old >> 16) != (old & 0xffff)) > return false; > > return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc > */ > }
This approach requires two loads (atomic_read() and cmpxchg()), which is not required. Detecting this pattern and optimizing it in a compiler is quite unlikely. A bit less generic solution would be to wrap the LL/SC (would be mandatory in this case) instructions and do something like this: uint32_t __smp_load_acquire_reserved(void*); int __smp_store_release_conditional(void*, uint32_t); typedef union { uint32_t v32; struct { uint16_t owner; uint16_t next; }; } arch_spinlock_t; int trylock(arch_spinlock_t *lock) { arch_spinlock_t l; int success; do { l.v32 = __smp_load_acquire_reserved(lock); if (l.owner != l.next) return 0; l.next++; success = __smp_store_release_conditional(lock, l.v32); } while (!success); return success; } But here we can't tell the compiler to optimize the code between LL and SC... > > That will try and do the full LL/SC loop, because it wants to complete > the cmpxchg, but in generic code we have no other option. > > (Is this what C11's weak cmpxchg is for?)