Introduce support for the LPASS LPI pin controller for the Qualcomm SM6350 SoC, by adding the dt-bindings, driver, dts bits and enabling it in the arm64 defconfig.
The custom slew offset for gpio14 is described as "qcom,lpi-slew-base-tbl" in the downstream dts[0]. I've tried to find some reasonable solution to have this handled correctly in the patches here, but suggestions are welcome how to improve the situation. There's of course several ways to implement a solution for this. [0] https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/refs/heads/kernel/13/fp4/qcom/lagoon-lpi.dtsi#25 Signed-off-by: Luca Weiss <[email protected]> --- Luca Weiss (5): dt-bindings: pinctrl: qcom: Add SM6350 LPI pinctrl pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control pinctrl: qcom: Add SM6350 LPASS LPI TLMM arm64: dts: qcom: sm6350: add LPASS LPI pin controller arm64: defconfig: Enable LPASS LPI pin controller for SM6350 .../pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml | 124 +++++++++++++++++ arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 +++++++++ arch/arm64/configs/defconfig | 1 + drivers/pinctrl/qcom/Kconfig | 9 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 20 +++ drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c | 149 +++++++++++++++++++++ 8 files changed, 372 insertions(+) --- base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2 change-id: 20260128-sm6350-lpi-tlmm-bdca4deb5641 Best regards, -- Luca Weiss <[email protected]>
