On 3/8/26 1:39 AM, Aelin Reidel wrote: > Add bindings documentation for the Fillmore (e.g. SM7450) Global Clock > Controller. > > Signed-off-by: Aelin Reidel <[email protected]> > --- > .../bindings/clock/qcom,fillmore-gcc.yaml | 60 +++++++ > include/dt-bindings/clock/qcom,fillmore-gcc.h | 195 > +++++++++++++++++++++ > 2 files changed, 255 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,fillmore-gcc.yaml > b/Documentation/devicetree/bindings/clock/qcom,fillmore-gcc.yaml > new file mode 100644 > index > 0000000000000000000000000000000000000000..0eb12a52968edc7961681f0e965b4d6da0858b9c > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,fillmore-gcc.yaml > @@ -0,0 +1,60 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,fillmore-gcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Global Clock & Reset Controller on Fillmore > + > +maintainers: > + - Aelin Reidel <[email protected]> > + > +description: | > + Qualcomm global clock control module provides the clocks, resets and power > + domains on Fillmore. > + > + See also: include/dt-bindings/clock/qcom,fillmore-gcc.h > + > +properties: > + compatible: > + const: qcom,fillmore-gcc > + > + clocks: > + items: > + - description: Board XO source > + - description: Sleep clock source > + - description: PCIE 0 Pipe clock source > + - description: UFS Phy Rx symbol 0 clock source > + - description: UFS Phy Rx symbol 1 clock source > + - description: UFS Phy Tx symbol 0 clock source > + - description: USB3 Phy wrapper pipe clock source > + > +required: > + - compatible > + - clocks > + - '#power-domain-cells' > + > +allOf: > + - $ref: qcom,gcc.yaml# > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,rpmh.h> > + clock-controller@100000 { > + compatible = "qcom,fillmore-gcc"; > + reg = <0x00100000 0x1f4200>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>, > + <&pcie0_phy>, > + <&ufs_mem_phy 0>, > + <&ufs_mem_phy 1>, > + <&ufs_mem_phy 2>, > + <&usb_1_qmpphy>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > +... > diff --git a/include/dt-bindings/clock/qcom,fillmore-gcc.h > b/include/dt-bindings/clock/qcom,fillmore-gcc.h > new file mode 100644 > index > 0000000000000000000000000000000000000000..1e78a429a93ab5e73f2454812cb904e2a9a14fc3 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,fillmore-gcc.h > @@ -0,0 +1,195 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2020, The Linux Foundation. All rights reserved. > + * Copyright (c) 2025, Aelin Reidel <[email protected]> > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7450_H > +#define _DT_BINDINGS_CLK_QCOM_GCC_SM7450_H
Ugh, I only noticed now after sending that this leftover is still in here. Consider it fixed in v2. Best regards, Aelin > + > +/* GCC HW clocks */ > +#define PCIE_0_PIPE_CLK 1 > +#define UFS_PHY_RX_SYMBOL_0_CLK 2 > +#define UFS_PHY_RX_SYMBOL_1_CLK 3 > +#define UFS_PHY_TX_SYMBOL_0_CLK 4 > +#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 5 <snip>
