* Andi Kleen <[EMAIL PROTECTED]> wrote:
> On Thu, Feb 07, 2008 at 08:13:37PM +0100, Ingo Molnar wrote:
> >
> > * Andi Kleen <[EMAIL PROTECTED]> wrote:
> >
> > > [probably stable material too]
> > >
> > > Use global TLB flushes in MTRR code
> > >
> > > Obviously kernel mappings should be flushed here too.
> >
> > no, your patch is not needed:
>
> Yes you're right. Thanks makes more sense. The weird style fooled
> me.
>
> It seems to come from the pseudo code in the Intel manual, but I think
> it would be still cleaner/more idiomatic to use two __flush_tlb_all()
> and remove the explicit code. The only drawback would be some more cr4
> accesses, which does not seem like a big issue.
>
> Updated patch follows.
... and this patch of yours breaks MTRR setting subtly:
> - /* Save value of CR4 and clear Page Global Enable (bit 7) */
> - if ( cpu_has_pge ) {
> - cr4 = read_cr4();
> - write_cr4(cr4 & ~X86_CR4_PGE);
> - }
> -
> - /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
> - __flush_tlb();
> + /* Flush all TLBs */
> + __flush_tlb_all();
because it's not just an open-coded __tlb_flush_all(), it _disables PGE
and keeps it so while the MTRR's are changed on all CPUs_.
Your patch adds __flush_tlb_all() which re-enables the PGE bit in cr4,
see asm-x86/tlbflush.h:
/* clear PGE */
write_cr4(cr4 & ~X86_CR4_PGE);
/* write old PGE again and flush TLBs */
write_cr4(cr4);
so we'll keep PGE enabled during the MTRR setting - which changes
behavior.
Ingo
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