* Andi Kleen <[EMAIL PROTECTED]> wrote:
> > > It changes behaviour in some minor ways but I don't think it makes
> > > any difference. PGE only influences TLB flushes (according to its
> > > specification) and all the TLB flushes still run with PGE
> > > disabled.
> >
> > now that i pointed out the difference, your position changed to
> > "changes behavior in minor ways" ;-)
>
> The instruction stream changes (more cr* accesses), but the actual
> flushes do not. [...]
You are still dead wrong. You refuse to realize the _obvious_ and
_fundamental_ thing that the PGE bit does: it enables global TLBs while
we change MTRRs!
That would be a completely new and totally untested modus operandi for a
large array of x86 CPUs. You should read the Intel manual about the
recommended way to change MTRRs (Vol. 3A 10-41) - it describes disabling
the PGE during MTRR changes if it's enabled. The primary purpose of that
is of course to flush the TLB entries - but still it's documented that
way and the current code does it that way. It would be rather stupid for
us to do otherwise: we simply cannot guarantee that x86 CPUs that
implement MTRRs and PGE have no undocumented or _unknown_ erratas in
this area. It _might_ be fine, while what you say is that it _is_ fine -
which we simply cannot know. (And yes, there are documented CPU erratas
related to global TLBs and MTRR's, so this area is far from being an
unwritten page.)
So i refuse to apply such a pointless and risky "cleanup" patch from you
to arch/x86 [which increases code size as well], _especially_ given how
many times i've explained this very issue to you already and especially
because you continue to mislead about the true effects of the patch.
Ingo
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