On 2026/4/9 15:42, Mark Rutland wrote:
> On Fri, Mar 20, 2026 at 06:42:20PM +0800, Jinjie Ruan wrote:
>> Currently, x86, ARM64, s390, and LoongArch all define and use
>> TIF_SINGLESTEP to track single-stepping state.
>
> Do the architectures actually use the flag in the same way?
As far as I know, the behavior of setting and clearing the
TIF_SINGLESTEP flag is consistent across these architectures, at least
within the ptrace handling logic of user_enable_single_step() and
user_disable_single_step().
>
> I'd expect that this is used subtly differently across those
> architectures, and so isn't necessarily generic.
>
>> Since this flag is shared across multiple major architectures and serves
>> a common purpose in the generic entry/exit paths, move TIF_SINGLESTEP
>> into the generic Thread Information Flags (TIF) infrastructure.
>>
>> This consolidation reduces architecture-specific boilerplate code and
>> ensures consistency for generic features that rely on single-step
>> state tracking.
>
> Is it necessary to make this generic in order to move to generic irq
> flags? I'd expect that generic code cannot make use of this due to the
> different semantics across architectures, as noted abobve.
>
> I think it's probably better to keep this architecture-specific for now,
> where architectures can clearly define how they're using this bit.
Hi Mark,
Thank you for the feedback. You are maybe right, and your concern aligns
with the original intent behind the generic TIF infrastructure.
I noticed that when the generic TIF infrastructure was first introduced
(see commit 29589343488e: "asm-generic: Provide generic TIF
infrastructure"), it explicitly mentioned:
"This could probably be extended by TIF_SINGLESTEP and BLOCKSTEP, but
those are only used in architecture specific code. So leave them alone
for now."
It seems that moving TIF_SINGLESTEP to generic TIF bits at this stage is
indeed premature. Furthermore, in the generic entry implementation, the
single-step exit handling is actually managed by
SYSCALL_WORK_SYSCALL_EXIT_TRAP rather than directly relying on a generic
TIF_SINGLESTEP flag.
Best regards,
Jinjie
>
> Am I missing some reason why it's necessary to make this generic?
>
> Mark.
>
>> Cc: Thomas Gleixner <[email protected]>
>> Reviewed-by: Kevin Brodsky <[email protected]>
>> Reviewed-by: Linus Walleij <[email protected]>
>> Reviewed-by: Yeoreum Yun <[email protected]>
>> Acked-by: Heiko Carstens <[email protected]> # s390
>> Signed-off-by: Jinjie Ruan <[email protected]>
>> ---
>> arch/loongarch/include/asm/thread_info.h | 11 +++++------
>> arch/s390/include/asm/thread_info.h | 7 +++----
>> arch/x86/include/asm/thread_info.h | 6 ++----
>> include/asm-generic/thread_info_tif.h | 5 +++++
>> 4 files changed, 15 insertions(+), 14 deletions(-)
>>
>> diff --git a/arch/loongarch/include/asm/thread_info.h
>> b/arch/loongarch/include/asm/thread_info.h
>> index 4d7117fcdc78..a2ec87f18e1d 100644
>> --- a/arch/loongarch/include/asm/thread_info.h
>> +++ b/arch/loongarch/include/asm/thread_info.h
>> @@ -70,6 +70,7 @@ register unsigned long current_stack_pointer
>> __asm__("$sp");
>> */
>> #define HAVE_TIF_NEED_RESCHED_LAZY
>> #define HAVE_TIF_RESTORE_SIGMASK
>> +#define HAVE_TIF_SINGLESTEP
>>
>> #include <asm-generic/thread_info_tif.h>
>>
>> @@ -82,11 +83,10 @@ register unsigned long current_stack_pointer
>> __asm__("$sp");
>> #define TIF_32BIT_REGS 21 /* 32-bit general purpose
>> registers */
>> #define TIF_32BIT_ADDR 22 /* 32-bit address space */
>> #define TIF_LOAD_WATCH 23 /* If set, load watch registers
>> */
>> -#define TIF_SINGLESTEP 24 /* Single Step */
>> -#define TIF_LSX_CTX_LIVE 25 /* LSX context must be preserved */
>> -#define TIF_LASX_CTX_LIVE 26 /* LASX context must be preserved */
>> -#define TIF_USEDLBT 27 /* LBT was used by this task this
>> quantum (SMP) */
>> -#define TIF_LBT_CTX_LIVE 28 /* LBT context must be preserved */
>> +#define TIF_LSX_CTX_LIVE 24 /* LSX context must be preserved */
>> +#define TIF_LASX_CTX_LIVE 25 /* LASX context must be preserved */
>> +#define TIF_USEDLBT 26 /* LBT was used by this task this
>> quantum (SMP) */
>> +#define TIF_LBT_CTX_LIVE 27 /* LBT context must be preserved */
>>
>> #define _TIF_NOHZ BIT(TIF_NOHZ)
>> #define _TIF_USEDFPU BIT(TIF_USEDFPU)
>> @@ -96,7 +96,6 @@ register unsigned long current_stack_pointer
>> __asm__("$sp");
>> #define _TIF_32BIT_REGS BIT(TIF_32BIT_REGS)
>> #define _TIF_32BIT_ADDR BIT(TIF_32BIT_ADDR)
>> #define _TIF_LOAD_WATCH BIT(TIF_LOAD_WATCH)
>> -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
>> #define _TIF_LSX_CTX_LIVE BIT(TIF_LSX_CTX_LIVE)
>> #define _TIF_LASX_CTX_LIVE BIT(TIF_LASX_CTX_LIVE)
>> #define _TIF_USEDLBT BIT(TIF_USEDLBT)
>> diff --git a/arch/s390/include/asm/thread_info.h
>> b/arch/s390/include/asm/thread_info.h
>> index 1bcd42614e41..95be5258a422 100644
>> --- a/arch/s390/include/asm/thread_info.h
>> +++ b/arch/s390/include/asm/thread_info.h
>> @@ -61,6 +61,7 @@ void arch_setup_new_exec(void);
>> */
>> #define HAVE_TIF_NEED_RESCHED_LAZY
>> #define HAVE_TIF_RESTORE_SIGMASK
>> +#define HAVE_TIF_SINGLESTEP
>>
>> #include <asm-generic/thread_info_tif.h>
>>
>> @@ -69,15 +70,13 @@ void arch_setup_new_exec(void);
>> #define TIF_GUARDED_STORAGE 17 /* load guarded storage control block */
>> #define TIF_ISOLATE_BP_GUEST 18 /* Run KVM guests with isolated
>> BP */
>> #define TIF_PER_TRAP 19 /* Need to handle PER trap on
>> exit to usermode */
>> -#define TIF_SINGLESTEP 21 /* This task is single stepped
>> */
>> -#define TIF_BLOCK_STEP 22 /* This task is block stepped */
>> -#define TIF_UPROBE_SINGLESTEP 23 /* This task is uprobe single
>> stepped */
>> +#define TIF_BLOCK_STEP 20 /* This task is block stepped */
>> +#define TIF_UPROBE_SINGLESTEP 21 /* This task is uprobe single
>> stepped */
>>
>> #define _TIF_ASCE_PRIMARY BIT(TIF_ASCE_PRIMARY)
>> #define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE)
>> #define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST)
>> #define _TIF_PER_TRAP BIT(TIF_PER_TRAP)
>> -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
>> #define _TIF_BLOCK_STEP BIT(TIF_BLOCK_STEP)
>> #define _TIF_UPROBE_SINGLESTEP BIT(TIF_UPROBE_SINGLESTEP)
>>
>> diff --git a/arch/x86/include/asm/thread_info.h
>> b/arch/x86/include/asm/thread_info.h
>> index 0067684afb5b..f59072ba1473 100644
>> --- a/arch/x86/include/asm/thread_info.h
>> +++ b/arch/x86/include/asm/thread_info.h
>> @@ -98,9 +98,8 @@ struct thread_info {
>> #define TIF_IO_BITMAP 22 /* uses I/O bitmap */
>> #define TIF_SPEC_FORCE_UPDATE 23 /* Force speculation MSR update
>> in context switch */
>> #define TIF_FORCED_TF 24 /* true if TF in eflags
>> artificially */
>> -#define TIF_SINGLESTEP 25 /* reenable singlestep on user
>> return*/
>> -#define TIF_BLOCKSTEP 26 /* set when we want
>> DEBUGCTLMSR_BTF */
>> -#define TIF_ADDR32 27 /* 32-bit address space on 64 bits */
>> +#define TIF_BLOCKSTEP 25 /* set when we want
>> DEBUGCTLMSR_BTF */
>> +#define TIF_ADDR32 26 /* 32-bit address space on 64 bits */
>>
>> #define _TIF_SSBD BIT(TIF_SSBD)
>> #define _TIF_SPEC_IB BIT(TIF_SPEC_IB)
>> @@ -112,7 +111,6 @@ struct thread_info {
>> #define _TIF_SPEC_FORCE_UPDATE BIT(TIF_SPEC_FORCE_UPDATE)
>> #define _TIF_FORCED_TF BIT(TIF_FORCED_TF)
>> #define _TIF_BLOCKSTEP BIT(TIF_BLOCKSTEP)
>> -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
>> #define _TIF_ADDR32 BIT(TIF_ADDR32)
>>
>> /* flags to check in __switch_to() */
>> diff --git a/include/asm-generic/thread_info_tif.h
>> b/include/asm-generic/thread_info_tif.h
>> index da1610a78f92..b277fe06aee3 100644
>> --- a/include/asm-generic/thread_info_tif.h
>> +++ b/include/asm-generic/thread_info_tif.h
>> @@ -48,4 +48,9 @@
>> #define TIF_RSEQ 11 // Run RSEQ fast path
>> #define _TIF_RSEQ BIT(TIF_RSEQ)
>>
>> +#ifdef HAVE_TIF_SINGLESTEP
>> +#define TIF_SINGLESTEP 12 /* reenable singlestep on user
>> return*/
>> +#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
>> +#endif
>> +
>> #endif /* _ASM_GENERIC_THREAD_INFO_TIF_H_ */
>> --
>> 2.34.1
>>
>
