From: Antony Kurniawan Soemardi <[email protected]> Add the Shared Memory State Machine node to coordinate state transitions between the Applications processor and the Riva subsystem.
Tested-by: Rudraksha Gupta <[email protected]> Signed-off-by: Antony Kurniawan Soemardi <[email protected]> --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 218cf3158dfb..107c5613aa4a 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -109,6 +109,31 @@ smem { hwlocks = <&sfpb_mutex 3>; }; + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&l2cc 8 4>; + qcom,ipc-2 = <&l2cc 8 14>; + qcom,ipc-3 = <&l2cc 8 23>; + qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + wcnss_smsm: wcnss@3 { + reg = <3>; + interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { compatible = "simple-bus"; ranges; @@ -455,6 +480,11 @@ clock-controller@4000000 { "hdmipll"; }; + sps_sic_non_secure: interrupt-controller@12100000 { + compatible = "qcom,msm8960-sps-sic", "syscon"; + reg = <0x12100000 0x10000>; + }; + sdcc3: mmc@12180000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x12180000 0x2000>; -- 2.34.1
