On 4/13/26 10:55 AM, Luca Weiss wrote: > Hi Konrad, > > On Thu Jan 29, 2026 at 12:19 PM CET, Konrad Dybcio wrote: >> On 1/29/26 9:32 AM, Luca Weiss wrote: >>> On Wed Jan 28, 2026 at 11:16 PM CET, Dmitry Baryshkov wrote: >>>> On Wed, Jan 28, 2026 at 01:26:52PM +0100, Luca Weiss wrote: >>>>> Add LPASS LPI pinctrl node required for audio functionality on SM6350. >>>>> >>>>> Signed-off-by: Luca Weiss <[email protected]> >>>>> --- >>>>> arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 >>>>> ++++++++++++++++++++++++++++++++++++ >>>>> 1 file changed, 66 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> index 9f9b9f9af0da..b1fb6c812da7 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> @@ -1448,6 +1448,72 @@ compute-cb@5 { >>>>> }; >>>>> }; >>>>> >>>>> + lpass_tlmm: pinctrl@33c0000 { >>>>> + compatible = "qcom,sm6350-lpass-lpi-pinctrl"; >>>>> + reg = <0x0 0x033c0000 0x0 0x20000>, >>>>> + <0x0 0x03550000 0x0 0x10000>; >>>>> + gpio-controller; >>>>> + #gpio-cells = <2>; >>>>> + gpio-ranges = <&lpass_tlmm 0 0 15>; >>>>> + >>>>> + clocks = <&q6afecc LPASS_HW_MACRO_VOTE >>>>> LPASS_CLK_ATTRIBUTE_COUPLE_NO>, >>>>> + <&q6afecc LPASS_HW_DCODEC_VOTE >>>>> LPASS_CLK_ATTRIBUTE_COUPLE_NO>; >>>>> + clock-names = "core", >>>>> + "audio"; >>>>> + >>>>> + i2s1_active: i2s1-active-state { >>>>> + clk-pins { >>>>> + pins = "gpio6"; >>>>> + function = "i2s1_clk"; >>>>> + drive-strength = <8>; >>>>> + bias-disable; >>>>> + output-high; >>>> >>>> This looks suspicious for the clock pin. >>>> >>>>> + }; >>>>> + >>>>> + ws-pins { >>>>> + pins = "gpio7"; >>>>> + function = "i2s1_ws"; >>>>> + drive-strength = <8>; >>>>> + bias-disable; >>>>> + output-high; >>>> >>>> The same >>>> >>>>> + }; >>>>> + >>>>> + data-pins { >>>>> + pins = "gpio8", "gpio9"; >>>>> + function = "i2s1_data"; >>>>> + drive-strength = <8>; >>>>> + bias-disable; >>>>> + output-high; >>>> >>>> And here. >>> >>> I've taken this pinctrl from downstream lagoon-lpi.dtsi. There the >>> active config for these pins have "output-high;" set. >>> >>> And fwiw this pinctrl works fine at runtime for driving the speaker. >> >> I tried to find an answer. >> >> A doc for this SoC says that i2s clock pins should be at output-low >> (2 mA) when muxed to the i2s_xxx function, with no information about >> bias settings (perhaps bias-disable), and in sleep they should be the >> same (minus the drive strength note, but 2mA is the lowest setting) >> >> I am further confused because the output-enable bit in the cfg >> register specifically says "when in GPIO mode" > > Thanks for checking. > > What should we do here now? Follow what you found in the docs, or follow > what downstream is doing (8ma output-high)? > > https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/refs/heads/int/15/fp4/qcom/lagoon-lpi.dtsi#219 > > I think apart from this question, this patchset should be ready to land.
I think I'm OK with following downstream. If we make any discoveries wrt docs, we'll likely need a mass fixup anyway, so Reviewed-by: Konrad Dybcio <[email protected]> adding +Srini for awareness Konrad
