On Thu, Jun 11, 2026 at 04:12:46PM -0400, Guodong Xu wrote: > From: Qingwei Hu <[email protected]> > > Zic64b mandates 64-byte naturally aligned cache blocks and is a > mandatory extension of the RVA22 and RVA23 profiles. Allocate a > RISCV_ISA_EXT_ZIC64B id, parse "zic64b" from the ISA string with a > validate callback that requires each cbom/cbop/cboz cache block size to > be 64 bytes when it is present, and export it through hwprobe. > > Link: > https://lists.riscv.org/g/tech-unprivileged/topic/question_about_zic64b_and/119631059 > Signed-off-by: Qingwei Hu <[email protected]> > Co-developed-by: Guodong Xu <[email protected]> > Signed-off-by: Guodong Xu <[email protected]> > --- > v4: > - Credit Qingwei Hu's earlier Zic64b cpufeature patch: set him as > author, with Co-developed-by (Guodong Xu). > - Validate only the cbom/cbop/cboz block sizes that are present; Zic64b > does not imply the CMO extensions (Conor, Qingwei, Greg). > - Add a Link: to Greg's confirmation on the tech-unprivileged list. > - Add the missing blank line before the ZIC64B hwprobe.rst entry > (Andrew). > - Did not carry Andrew Jones's v3 Reviewed-by: the validation was > rewritten (present block sizes only) and the patch is now authored by > Qingwei, so it warrants a fresh review. > v3: New patch. > --- > Documentation/arch/riscv/hwprobe.rst | 4 ++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > arch/riscv/kernel/cpufeature.c | 19 +++++++++++++++++++ > arch/riscv/kernel/sys_hwprobe.c | 1 + > 5 files changed, 26 insertions(+) >
Reviewed-by: Andrew Jones <[email protected]>
