On Mon, 11 Feb 2008 16:12:56 +0100 Andi Kleen <[EMAIL PROTECTED]> wrote:
> On Monday 11 February 2008 16:04:30 Arjan van de Ven wrote: > > On Mon, 11 Feb 2008 10:50:22 +0100 (CET) > > Andi Kleen <[EMAIL PROTECTED]> wrote: > > > > > > > > [2.6.25 candidate I believe] > > > > > > The specification of SS in the public manuals is a little unclear, > > > but I got confirmation from Intel that SS implies that there is no > > > cache flush needed on caching attribute changes. > > > > I'm hearing slightly different information, but am still chasing > > this one. > > 10.12.8 in the ia32 manual volume 3a says: > > " > When remapping a page that was previously mapped as a cacheable > memory type to a WC page, an operating system can avoid this type of > aliasing by doing the following: > ... > > 3. Create a new mapping to the same physical address with a new > memory type, for instance, WC. > 4. Flush the caches on all processors that may have used the mapping > previously. Note on processors that support self-snooping, CPUID > feature flag bit 27, this > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > step is unnecessary. ^^^^^^^^^^^^^^^^^^^^ > " > > That is exactly the situation in pageattr.c. You're saying the manual > is wrong here? I'm saying that we are not following step 2 (marking the pages not present) so 3 and 4 aren't all too relevant. As I said before I've asked internally about this and got mixed answers so I'm still chasing it down. -- If you want to reach me at my work email, use [EMAIL PROTECTED] For development, discussion and tips for power savings, visit http://www.lesswatts.org -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/