On 2026/8/17 15:24, Chen Pei wrote:
Now that the riscv64 JIT supports signed arena loads
(BPF_PROBE_MEM32SX), enable the arena LDSX tests on riscv64:
add JIT disassembly assertions for arena_ldsx_disasm (arena base in
s7, add into t2, sign-extending lw/lh/lb loads) and run
arena_ldsx_exception and arena_ldsx_s8/s16/s32 on riscv64.

Signed-off-by: Chen Pei <[email protected]>
---
  .../testing/selftests/bpf/progs/verifier_ldsx.c | 17 +++++++++++++++++
  1 file changed, 17 insertions(+)

diff --git a/tools/testing/selftests/bpf/progs/verifier_ldsx.c 
b/tools/testing/selftests/bpf/progs/verifier_ldsx.c
index 41340877dc9d..ed0a0f159bc1 100644
--- a/tools/testing/selftests/bpf/progs/verifier_ldsx.c
+++ b/tools/testing/selftests/bpf/progs/verifier_ldsx.c
@@ -286,6 +286,19 @@ __jited("add  x11, x0, x28")
  __jited("ldrsh   x22, [x11, #0x18]")
  __jited("add     x11, x0, x28")
  __jited("ldrsb   x22, [x11, #0x20]")
+__arch_riscv64
+__jited("add      t2, a5, s7")
+__jited("lw       s3, 0x10(t2)")
+__jited("add      t2, a5, s7")
+__jited("lh       s3, 0x18(t2)")
+__jited("add      t2, a5, s7")
+__jited("lb       s3, 0x20(t2)")
+__jited("add      t2, a0, s7")
+__jited("lw       s4, 0x10(t2)")
+__jited("add      t2, a0, s7")
+__jited("lh       s4, 0x18(t2)")
+__jited("add      t2, a0, s7")
+__jited("lb       s4, 0x20(t2)")
  __naked void arena_ldsx_disasm(void *ctx)
  {
        asm volatile (
@@ -317,6 +330,7 @@ __description("Arena LDSX Exception")
  __success __retval(0)
  __arch_x86_64
  __arch_arm64
+__arch_riscv64
  __naked void arena_ldsx_exception(void *ctx)
  {
        asm volatile (
@@ -338,6 +352,7 @@ __description("Arena LDSX, S8")
  __success __retval(-1)
  __arch_x86_64
  __arch_arm64
+__arch_riscv64
  __naked void arena_ldsx_s8(void *ctx)
  {
        asm volatile (
@@ -369,6 +384,7 @@ __description("Arena LDSX, S16")
  __success __retval(-1)
  __arch_x86_64
  __arch_arm64
+__arch_riscv64
  __naked void arena_ldsx_s16(void *ctx)
  {
        asm volatile (
@@ -400,6 +416,7 @@ __description("Arena LDSX, S32")
  __success __retval(-1)
  __arch_x86_64
  __arch_arm64
+__arch_riscv64
  __naked void arena_ldsx_s32(void *ctx)
  {
        asm volatile (

Reviewed-by: Pu Lehui <[email protected]>

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