On Mon, 18 Feb 2008 13:31:48 +0100 Andi Kleen <[EMAIL PROTECTED]> wrote:
> Arjan van de Ven <[EMAIL PROTECTED]> writes: > > > > the initial plan was for a depreciation period. Sadly it was > > untenable since the API was changing entirely to fix bugs and add a > > really important feature (the ability to clflush the exact range > > rather than wbinvd'ing the caches of all cpus in the system), > > Just for the record: I posted full patches to implement clflush > support some time ago without changing any exported API. So your > claims that changing the API was needed to implement CLFLUSH are not > correct. yeah of course it is possible to make things "smart" by having hidden state. doesn't make it right. > > Also I believe some assumptions behind the new API are faulty (in > particular that the caller doesn't fully own the to be changed pages) > and make it actually impossible to implement the cache attribute PTE > changing operation fully correct according to the Intel x86 manual > (which requires temporary unmap) the Intel x86 manual explicitly only has a temporary unmap when going from a cached state to a write-combining state. Any other transition does not require an unmap. Which makes this not impossible, all a cached->WC transition needs to do is go via an intermediate UC state and the really expensive process from the manual is not needed. -- If you want to reach me at my work email, use [EMAIL PROTECTED] For development, discussion and tips for power savings, visit http://www.lesswatts.org -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/