Hi! On Wednesday 20 February 2008, you wrote: > A spi transfer with zero length is not invalid. Such transfer can be > used to achieve delay before first CLK edge after chipselect assertion. How long will be that delay?
If they are really users of that kind of thing, this should be fixed by adding a "delay_us_before_xfer" field in the struct spi_transfer. Have you tested it? I think if you start a transfer with 0 len, the ENDRX bit will never rise, however, I'm not sure about this. Regards Marc -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
