From: Stephen Warren <swar...@nvidia.com>
When suspending, we set up the wake mask registers as required. Some
chips don't have separate wake mask registers, so they set mask_base
equal to wake_base. In that case, when resuming, we re-program the
interrupt enable registers based on enable state rather than wake state.
Signed-off-by: Stephen Warren <swar...@nvidia.com>
---
drivers/base/regmap/regmap-irq.c | 62 ++++++++++++++++++++++++++++++++++++++
1 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index c7e5b18..6bb4364 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -129,6 +129,61 @@ static int regmap_irq_set_wake(struct irq_data *data,
unsigned int on)
return 0;
}
+static void regmap_irq_suspend(struct irq_data *data)
+{
+ struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
+ struct regmap *map = d->map;
+ int i, ret;
+ u32 reg;
+
+ if (!d->wake_buf)
+ return;
+
+ /*
+ * Mask all non-wakeup interrupts. This writes to wake_base, which
+ * may be identical to mask_base.
+ */
+ for (i = 0; i < d->chip->num_regs; i++) {
+ reg = d->chip->wake_base +
+ (i * map->reg_stride * d->irq_reg_stride);
+ ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i],
+ d->wake_buf[i]);
+ if (ret != 0)
+ dev_err(d->map->dev, "Failed to sync masks in %x\n",
+ reg);
+ }
+}
+
+static void regmap_irq_resume(struct irq_data *data)
+{
+ struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
+ struct regmap *map = d->map;
+ int i, ret;
+ u32 reg;
+
+ if (!d->wake_buf)
+ return;
+
+ /*
+ * If mask_base is a separate register to wake_base, then
+ * regmap_irq_suspend() didn't trash the enable registers,
+ * so there's no need to restore them.
+ */
+ if (d->chip->mask_base != d->chip->wake_base)
+ return;
+
+ /* Mask all non-enabled interrupts */
+ for (i = 0; i < d->chip->num_regs; i++) {
+ reg = d->chip->mask_base +
+ (i * map->reg_stride * d->irq_reg_stride);
+ ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i],
+ d->mask_buf[i]);
+ if (ret != 0)
+ dev_err(d->map->dev, "Failed to sync masks in %x\n",
+ reg);
+ }
+}
+
static struct irq_chip regmap_irq_chip = {
.name = "regmap",
.irq_bus_lock = regmap_irq_lock,
@@ -136,6 +191,8 @@ static struct irq_chip regmap_irq_chip = {
.irq_disable = regmap_irq_disable,
.irq_enable = regmap_irq_enable,
.irq_set_wake = regmap_irq_set_wake,
+ .irq_suspend = regmap_irq_suspend,
+ .irq_resume = regmap_irq_resume,
};
static irqreturn_t regmap_irq_thread(int irq, void *d)
@@ -314,6 +371,11 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int
irq_flags,
}
}
+ /* Wake is disabled by default */
+ if (d->wake_buf)
+ for (i = 0; i < chip->num_regs; i++)
+ d->wake_buf[i] = d->mask_buf_def[i];
+
if (irq_base)
d->domain = irq_domain_add_legacy(map->dev->of_node,
chip->num_irqs, irq_base, 0,
--
1.7.0.4
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