[PATCH 13/33] perf, x86: Avoid checkpointed counters causing excessive TSX aborts v3

[Andi Kleen]

From: Andi Kleen <a...@linux.intel.com>

With checkpointed counters there can be a situation where the counter
is overflowing, aborts the transaction, is set back to a non overflowing
checkpoint, causes interupt. The interrupt doesn't see the overflow
because it has been checkpointed.  This is then a spurious PMI, typically with a
ugly NMI message.  It can also lead to excessive aborts.

Avoid this problem by:
- Using the full counter width for counting counters (previous patch)
- Forbid sampling for checkpointed counters. It's not too useful anyways,
checkpointing is mainly for counting.
- On a PMI always set back checkpointed counters to zero.

v2: Add unlikely. Add comment
v3: Allow large sampling periods with CP for KVM
Signed-off-by: Andi Kleen <a...@linux.intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel.c |   33 ++++++++++++++++++++++++++++++++
 1 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c 
b/arch/x86/kernel/cpu/perf_event_intel.c
index 9bff694..bbd00cc 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1079,6 +1079,17 @@ static void intel_pmu_enable_event(struct perf_event 
*event)
 int intel_pmu_save_and_restart(struct perf_event *event)
 {
        x86_perf_event_update(event);
+       /*
+        * For a checkpointed counter always reset back to 0.  This
+        * avoids a situation where the counter overflows, aborts the
+        * transaction and is then set back to shortly before the
+        * overflow, and overflows and aborts again.
+        */
+       if (unlikely(event->hw.config & HSW_INTX_CHECKPOINTED)) {
+               /* No race with NMIs because the counter should not be armed */
+               wrmsrl(event->hw.event_base, 0);
+               local64_set(&event->hw.prev_count, 0);
+       }
        return x86_perf_event_set_period(event);
 }
 
@@ -1162,6 +1173,15 @@ again:
                x86_pmu.drain_pebs(regs);
        }
 
+       /*
+        * To avoid spurious interrupts with perf stat always reset checkpointed
+        * counters.
+        *
+        * XXX move somewhere else.
+        */
+       if (cpuc->events[2] && (cpuc->events[2]->hw.config & 
HSW_INTX_CHECKPOINTED))
+               status |= (1ULL << 2);
+
        for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
                struct perf_event *event = cpuc->events[bit];
 
@@ -1635,6 +1655,19 @@ static int hsw_hw_config(struct perf_event *event)
             ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
              event->attr.precise_ip > 0))
                return -EIO;
+       if (event->hw.config & HSW_INTX_CHECKPOINTED) {
+               /*
+                * Sampling of checkpointed events can cause situations where
+                * the CPU constantly aborts because of a overflow, which is
+                * then checkpointed back and ignored. Forbid checkpointing
+                * for sampling.
+                *
+                * But still allow a long sampling period, so that perf stat
+                * from KVM works.
+                */
+               if (event->attr.sample_period < 0x7fffffff)
+                       return -EIO;
+       }
        return 0;
 }
 
-- 
1.7.7.6

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