* Andi Kleen <a...@firstfloor.org> wrote:
> From: Andi Kleen <a...@linux.intel.com>
>
> Recent Intel CPUs like Haswell and IvyBridge have a new alternative MSR
> range for perfctrs that allows writing the full counter width. Enable this
> range if the hardware reports it using a new capability bit.
>
> This lowers the overhead of perf stat slightly because it has to do less
> interrupts to accumulate the counter value. On Haswell it also avoids some
> problems with TSX aborting when the end of the counter range is reached.
>
> v2: Print the feature at boot
> Reviewed-by: Stephane Eranian <eran...@google.com>
> Signed-off-by: Andi Kleen <a...@linux.intel.com>
> ---
> arch/x86/include/uapi/asm/msr-index.h | 3 +++
> arch/x86/kernel/cpu/perf_event.h | 1 +
> arch/x86/kernel/cpu/perf_event_intel.c | 7 +++++++
> 3 files changed, 11 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/include/uapi/asm/msr-index.h
> b/arch/x86/include/uapi/asm/msr-index.h
> index 433a59f..af41a77 100644
> --- a/arch/x86/include/uapi/asm/msr-index.h
> +++ b/arch/x86/include/uapi/asm/msr-index.h
> @@ -163,6 +163,9 @@
> #define MSR_KNC_EVNTSEL0 0x00000028
> #define MSR_KNC_EVNTSEL1 0x00000029
>
> +/* Alternative perfctr range with full access. */
> +#define MSR_IA32_PMC0 0x000004c1
> +
> /* AMD64 MSRs. Not complete. See the architecture manual for a more
> complete list. */
>
> diff --git a/arch/x86/kernel/cpu/perf_event.h
> b/arch/x86/kernel/cpu/perf_event.h
> index ded4667..adaa0b0 100644
> --- a/arch/x86/kernel/cpu/perf_event.h
> +++ b/arch/x86/kernel/cpu/perf_event.h
> @@ -278,6 +278,7 @@ union perf_capabilities {
> u64 pebs_arch_reg:1;
> u64 pebs_format:4;
> u64 smm_freeze:1;
> + u64 fw_write:1;
No brownies for obfuscation: that should be named
full_width_write, not a meaningless abbreviation that anyone
crossing the code could mistake as 'firewall write' or 'forward
write' or anything.
Also a comment line at the field should explain its meaning.
Thanks,
Ingo
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