On 6/24/2013 2:59 PM, Benjamin Herrenschmidt wrote:
On Mon, 2013-06-24 at 08:26 -0700, Arjan van de Ven wrote:
to bring the system back up if all cores in the whole system are idle and power
gated,
memory in SR etc... is typically < 250 usec (depends on the exact version
of the cpu etc). But the moment even one core is running, that core will keep
the system
out of such deep state, and waking up a consecutive entity is much faster
to bring just a core out of power gating is more in the 40 to 50 usec range
Out of curiosity, what happens to PCIe when you bring a package down
like this ?
PCIe devices can communicate latency requirements (LTR) if they need something
more aggressive than this; otherwise 250 usec afaik falls within what doesn't
break (devices need to cope with arbitrage/etc delays anyway)
and with PCIe link power management there are delays regardless; once a PCIe
link gets powered
back on the memory controller/etc also will come back online
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