On 30.7.2013 22.35, Borislav Petkov wrote: > On Tue, Jul 30, 2013 at 09:50:49PM +0300, Ilari Stenroth wrote: >> Does somebody know why arch/x86/kernel/cpu/intel.c has >> tlb_flushall_shift detection logic for Ivy Bridge CPU family but not >> for Haswell? Maybe intel_cacheinfo.c needs to be checked for Haswell >> updates too. > > Because someone needs to sit down and write it. Oh, and more > importantly, test it on real hardware. > > :-) >
Right :-) Can volunteer to test, only once I get a motherboard bug fixed. It runs only one core. Poor Supermicro X10SLH-F thinks Xeon E3-1265Lv3 has 1C2T :-/ Regs, Ilari Stenroth -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
