On Mon, Jul 29, 2013 at 11:29 PM, David Daney <[email protected]> wrote:
> From: David Daney <[email protected]> > > The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip > GPIO pins, this driver handles them all. Configuring the pins as > interrupt sources is handled elsewhere (OCTEON's irq handling code). > > Signed-off-by: David Daney <[email protected]> > --- > > Device tree binding defintions already exist for this device in > Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt I like this. Reviewed-by: Linus Walleij <[email protected]> I guess you will merge both patches through the MIPS arch tree? Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
