3.5.7.23 -stable review patch.  If anyone has any objections, please let me 
know.

------------------

From: Nithin Sujir <nsu...@broadcom.com>

commit 989038e217e94161862a959e82f9a1ecf8dda152 upstream.

Turning off led on port 0 of the 5719 serdes causes all other ports to
lose power and stop functioning. Add tg3_phy_led_bug() function to check
for this condition. We use a switch() in tg3_phy_led_bug() for
consistency with the tg3_phy_power_bug() function.

Signed-off-by: Nithin Nayak Sujir <nsu...@broadcom.com>
Signed-off-by: Michael Chan <mc...@broadcom.com>
Signed-off-by: David S. Miller <da...@davemloft.net>
[ luis: backported to 3.5:
  - use GET_ASIC_REV() macro instead of tg3_asic_rev() ]
Signed-off-by: Luis Henriques <luis.henriq...@canonical.com>
---
 drivers/net/ethernet/broadcom/tg3.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/tg3.c 
b/drivers/net/ethernet/broadcom/tg3.c
index 504b4f0..5e01182 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -2783,6 +2783,19 @@ static bool tg3_phy_power_bug(struct tg3 *tp)
        return false;
 }
 
+static bool tg3_phy_led_bug(struct tg3 *tp)
+{
+       switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
+       case ASIC_REV_5719:
+               if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
+                   !tp->pci_fn)
+                       return true;
+               return false;
+       }
+
+       return false;
+}
+
 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
 {
        u32 val;
@@ -2827,8 +2840,9 @@ static void tg3_power_down_phy(struct tg3 *tp, bool 
do_low_power)
                }
                return;
        } else if (do_low_power) {
-               tg3_writephy(tp, MII_TG3_EXT_CTRL,
-                            MII_TG3_EXT_CTRL_FORCE_LED_OFF);
+               if (!tg3_phy_led_bug(tp))
+                       tg3_writephy(tp, MII_TG3_EXT_CTRL,
+                                    MII_TG3_EXT_CTRL_FORCE_LED_OFF);
 
                val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
                      MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
-- 
1.8.3.2

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