On Sun, Oct 27, 2013 at 06:31:31PM +0100, Borislav Petkov wrote: > On Sun, Oct 27, 2013 at 05:51:59PM +0100, Andreas Werner wrote: > > Im currently working on an ethernet driver for our own ETH core. The > > problem is that one requirement is to not use DMA to transmit or > > receive the data. This means the that the ethernet buffers are not > > located in the main memory. They are located in the FPGA internal RAM. > > > > To transmit or receive a frame, i have to read or write to mmio to get > > the data. > > > > Intel has introduced the instruction "clflush" which can flush a cache > > line. I want to use the caches for those mmio (eth buffer) to speed > > up the transmit/receive and to transmit/receive using PCIe bursts > > (read/write). > > > > The problem was if i set the buffer to Write-Back and call clflush on > > those mmio-addresses, the system crashed without any output. > > But allocating a WB region and calling CLFLUSH right after writing > into it sounds like you want to allocate an UC region, no? Writing > into it will make sure the data has reached memory and is not in the > cache, basically what CLFLUSH does but by having it UC, this happens > automatically. > > So basically what ioremap_nocache does. > > > I found this articel > > http://software.intel.com/en-us/forums/topic/393070 > > > > After that i configured the transmit buffers to be Write-Combining > > (only write to that adresses) using ioremap_wc, and the receive > > buffers to be Write-Through (ioremap_cache + mtrr Write-Through + this > > kernel patch) everything worked as expected. > > Right, but this all sounds like you want to use ioremap_nocache which > makes your buffers UC. > > -- > Regards/Gruss, > Boris. > > Sent from a fat crate under my desk. Formatting is fine. > --
Maybe you missunderstood me. My configuration is: Transmit Buffers WC (only write to that buffer) i have PICe bursts on my tracer. Receive Buffers WT (only read to that buffer). I use clflush_cache_range before reading from that adresses and i have PCIe bursts on my tracer. With UC memory there are no PCIe bursts and my bandwidth is very slow. Best regards Andy -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/