On Fri, 2014-02-07 at 10:02 +0100, Torsten Duwe wrote: > > > > Can you pair lwarx with sthcx ? I couldn't immediately find the answer > > > > in the PowerISA doc. If so I think you can do better by being able to > > > > atomically load both tickets but only storing the head without affecting > > > > the tail. > > Can I simply write the half word, without a reservation, or will the HW caches > mess up the other half? Will it ruin the cache coherency on some > (sub)architectures?
Yes, you can, I *think* > > Plus, sthcx doesn't exist on all PPC chips. > > Which ones are lacking it? Do all have at least a simple 16-bit store? half word atomics (and byte atomics) are new, they've been added in architecture 2.06 I believe so it's fairly recent, but it's still worthwhile to investigate a way to avoid atomics on unlock on recent processors (we can use instruction patching if necessary based on CPU features) because there's definitely a significant cost in doing a larx/stcx. sequence on powerpc, way higher than our current unlock path of barrier + store. Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
