On Thu, 2014-02-13 at 12:05 +0200, Tomi Valkeinen wrote:
> On 13/02/14 11:03, Tomi Valkeinen wrote:
> > On 12/02/14 15:18, Tomi Valkeinen wrote:
> > 
> >> However, I hacked together the patch below, which "fixes" the issue for
> >> 96m and dss fclk. It sets the clock parents so that the x2 clocks are
> >> skipped, and makes the x2 clock nodes compatible with "unused", making
> >> them effectively disappear. I only verified dss fclk, so Christoph, can
> >> you verify the 96m clock?
> > 
> > Aaand the hack patch I sent is crap... We can't skip the x2 clock path,
> > as the dpll4_mNx2_ck clock nodes handle enable/disable bit, which is
> > present on 3630 also.
> > 
> > I think the best and simplest way to fix this is by setting the
> > multiplier in the dpll4_mNx2_mul_ck nodes to 1. I don't know why I
> > didn't think of it yesterday.
> > 
> > I have a bunch of other patches needed to get the clocks right, so I'll
> > send a series separately a bit later today.
> 
> I just sent the "OMAP: OMAP3 DSS related clock patches" series to l-o
> and arm lists, which hopefully solves issues discussed in this thread.

Yes, thanks Tomi. I tested your patch series on a83x board. 96m clock
and DSS-clocks are fine now. If you want, you can add my:

 Tested-by: Christoph Fritz <chf.fr...@googlemail.com>

to your series "OMAP: OMAP3 DSS related clock patches".

The only issue left on current mainline for a83x board is that twl4030
(tps65920) doesn't set VIO as on next-20140120.

 Thanks
  -- Christoph

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