(2014/04/11 21:23), Denys Vlasenko wrote: > On Fri, Apr 11, 2014 at 5:03 AM, Masami Hiramatsu > <masami.hiramatsu...@hitachi.com> wrote: >> At least, if we can trust Intel SDM, it says that depends >> on the operand-size (insn->opnd_bytes) and stack segment >> descriptor. Please check the SDM vol.1 6.2.2 Stack Alignment >> and vol.2a, 3.2 Instructions (A-M), CALL--Call Procedure. >> But we'd better check it on x86-32. > > I am past trusting CPU manuals on this one: > > By now I verified on the real hardware that AMD and Intel CPUs > handle this insn differently in 64-bit mode: Intel ignores 0x66 prefix. > AMD treats this insn the same as in 32-bit mode: as 16-bit insn. > > (Should I submit a patch adding comment about it > in x86-opcode-map.txt?)
Yeah, feel free to do so :) > So there is no universally "correct" way to emulate it. > > We, theoretically, can decode it differently *depending > on actual CPU(s) on the system*... do we really want > to go *that* far? I guess not. No I guess not too. If we start such thing, we need to cover other x86 variants too... And actually jump/callw is not a normal instructions. BTW, I can see that difference on AMD64 architecture programmers manual vol.3 appendix A. It seems that the difference is by design... Thank you, -- Masami HIRAMATSU Software Platform Research Dept. Linux Technology Center Hitachi, Ltd., Yokohama Research Laboratory E-mail: masami.hiramatsu...@hitachi.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
