From: Chew, Chiau Ee <chiau.ee.c...@intel.com> Hi,
BayTrail LPSS subsystem consists of one SPI host which can be PCI enumerated. PXA2XX PCI layer used to support only CE4100's SPI. Thus, we convert it into a generic PCI layer to add support for LPSS SPI as well. Since PCI mode LPSS SPI does not rely on common clock framework, we need a mechanism to pass in the host supported clock rate to core layer. Thus, we introduced a new member known as "max_clk_rate" under struct pxa2xx_spi_master which can be used in PCI glue layer to pass in host supported clock rate info. Chew, Chiau Ee (2): spi/pxa2xx-pci: Add PCI mode support for BayTrail LPSS SPI spi/pxa2xx-pci: Pass host clock rate info from PCI glue layer Documentation/spi/pxa2xx | 3 ++ drivers/spi/spi-pxa2xx-pci.c | 79 ++++++++++++++++++++++++++++++++-------- drivers/spi/spi-pxa2xx.c | 2 + include/linux/spi/pxa2xx_spi.h | 1 + 4 files changed, 70 insertions(+), 15 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
