On 04/22/2014 08:48 AM, Ben Skeggs wrote:
On Tue, Apr 22, 2014 at 4:03 AM, Ilia Mirkin <imir...@alum.mit.edu> wrote:
On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot <acour...@nvidia.com> wrote:
Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will
bytes or u32's? From the code, I'm guessing the latter. (Similar
concern about comment in the code.)
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot <acour...@nvidia.com>
Reviewed-by: Thierry Reding <tred...@nvidia.com>
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index e5b75f189988..013475c62986 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -894,6 +894,10 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32
fuc_base,
nv_wr32(priv, fuc_base + 0x0188, i >> 6);
nv_wr32(priv, fuc_base + 0x0184, code->data[i]);
}
+
+ /* code must be padded to 0x40 bytes */
+ for (; i & 0x3f; i++)
+ nv_wr32(priv, fuc_base + 0x0184, 0);
It's 256 bytes indeed.
Fixed, thanks!
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