On Thu, 8 May 2014, Feng Kan wrote:
> This change is made to preserve the GIC v2 bypass bits in the
> GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec).
> This code will preserve all bits configured by the bootload regarding
> v2 bypass group bits. In the X-Gene platform, the bypass functionality
> is not used and bypass bits should not be changed by the kernel gic
> code as it could lead to incorrect behavior.
>
> Signed-off-by: Vinayak Kale <vk...@apm.com>
> Acked-by: Anup Patel <apa...@apm.com>
> Signed-off-by: Feng Kan <f...@apm.com>
> ---
> V7: cleanup white spaces, remove export in gic.h, change if_up to static.
> V6: add gic_cpu_if_up function to replace macro used in v5
> V5: Use macro to replace read modify write of cpu_ctrl register.
> V4: Change to use bypass mask, change ot user more suitable variable name.
> drivers/irqchip/irq-gic.c | 30 +++++++++++++++++++++++++++---
> 1 files changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 4300b66..7e952c3 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -373,6 +373,20 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
> return mask;
> }
>
> +static void gic_cpu_if_up(void)
> +{
> + void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
> + u32 bypass;
> +
> + /*
> + * Preserve bypass disable bits to be written back later
> + */
> + bypass = readl(cpu_base + GIC_CPU_CTRL);
> + bypass &= 0x1e0;
Can we please use some reasonable defines instead of magic hex
constants?
It's not a new problem as the existing code is full of magic
numbers. But as a compensation for stealing so much of Marcs time for
this rather trivial endeavour, please create a patch series with two
patches:
1/2: Replace the existing magic constants in that code with reasonable
self explaining defines
2/2: Add your new stuff on top of it.
Thanks,
tglx
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