On 05/13/2014 03:50 PM, Doug Anderson wrote: ... > ...but then I found the true problem shows up when we transition > between very low frequencies on exynos, like between 200MHz and > 300MHz. While transitioning between frequencies the system > temporarily bumps over to the "switcher" PLL running at 800MHz while > waiting for the main PLL to stabilize. No CPUFREQ notification is > sent for that. That means there's a period of time when we're running > at 800MHz but loops_per_jiffy is calibrated at between 200MHz and > 300MHz. > > > I'm welcome to any suggestions for how to address this. It sorta > feels like it would be a common thing to have a temporary PLL during > the transition, ...
We definitely do that on Tegra for some cpufreq transitions. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
