The Global Interrupt Controller (GIC) present on certain MIPS systems
can be used to route external interrupts to individual VPEs and CPU
interrupt vectors. It also supports a timer and software-generated
interrupts.
Signed-off-by: Andrew Bresticker <abres...@chromium.org>
---
Changes from v1:
- moved from mips/ to interrupt-controller/
- removed interrupts and interrupt-parent properties
- added available-cpu-vectors property
- dropped third cell in interrupt specifier
---
.../bindings/interrupt-controller/mips-gic.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
new file mode 100644
index 0000000..81ca911
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
@@ -0,0 +1,39 @@
+MIPS Global Interrupt Controller (GIC)
+
+The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
+It also supports local (per-processor) interrupts and software-generated
+interrupts which can be used as IPIs.
+
+Required properties:
+- compatible : Should be "mti,global-interrupt-controller"
+- reg : Base address and length of the GIC registers.
+- interrupts : Core interrupts to which the GIC may route external interrupts.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt specifier. Should be 2.
+ - The first cell is the GIC interrupt number.
+ - The second cell encodes the interrupt flags.
+ See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
+ flags.
+- mti,available-cpu-vectors : Specifies the list of CPU interrupt vectors
+ to which the GIC may route interrupts. May contain up to 6 entries, one
+ for each of the CPU's hardware interrupt vectors. Valid values are 2 - 7.
+
+Example:
+
+ gic: interrupt-controller@1bdc0000 {
+ compatible = "mti,global-interrupt-controller";
+ reg = <0x1bdc0000 0x20000>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ mti,available-cpu-vectors = <2>, <3>, <4>, <5>;
+ };
+
+ uart@18101400 {
+ ...
+ interrupt-parent = <&gic>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+ ...
+ };
--
2.1.0.rc2.206.gedb03e5
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