Hi,
Some one has submitted a patch addressing this issue a few days ago.
The patch is now being cooked in the paulk's tree now, IIRC.
Thanks,
Jianyu Zhan
On Tue, Sep 16, 2014 at 4:51 PM, Yao Dongdong <yaodongd...@huawei.com> wrote:
> The table shows CPU2's sequence of events as "x = B; y = A;", but its comment
> followed
> described as "x = A; y = B;".
>
> Signed-off-by: Yao Dongdong <yaodongd...@huawei.com>
> ---
> Documentation/memory-barriers.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/memory-barriers.txt
> b/Documentation/memory-barriers.txt
> index a4de88f..9a46bbe 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -115,8 +115,8 @@ For example, consider the following sequence of events:
> CPU 1 CPU 2
> =============== ===============
> { A == 1; B == 2 }
> - A = 3; x = B;
> - B = 4; y = A;
> + A = 3; x = A;
> + B = 4; y = B;
>
> The set of accesses as seen by the memory system in the middle can be
> arranged
> in 24 different combinations:
> --
> 1.8.0.1
>
> --
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