On Tue, 2014-09-30 at 20:15 +0000, Jojy Varghese wrote: > > On 9/30/14 8:50 AM, "Guenter Roeck" <li...@roeck-us.net> wrote: > > >On Mon, Sep 29, 2014 at 06:31:06PM -0500, Scott Wood wrote: > >> Which specific chip and revision did you see this on? What is the value > >> in MCSR? > >> > >Jojy can answer that, at least for P5020. We have seen it on P5040 as > >well, > >though, so it is not just limited to one chip/revision. > > The specifics are: > PVR: 0x80240012 > Instruction that causes the MC exception: lwbrx > The faulty load address is also present in RB. So we could change the > logic to use that > instead of DEAR. What I don’t know is of there are other cases also which > escapes the current logic.
Could you find out what MCSR was when that happened? I'm most interested in whether MAV was set, but the other bits would be interesting as well. -Scott -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
