This changes the HSW events to be more inline with the other uarchs and removes the prefetch request bits from the read/write demands and into the prefetch demand.
Cc: Andi Kleen <[email protected]> Cc: Stephane Eranian <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: http://lkml.kernel.org/n/[email protected] --- arch/x86/kernel/cpu/perf_event_intel.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -539,16 +539,12 @@ static __initconst const u64 hsw_hw_cach * SNB_LLC_* is specified as 'reserved' in the SDM * but Andi added it anyhow, suggesting HSW/BDW have it just fine * - * XXX NHM/WSM/SNB/IVB don't have the PF/IFETCH bits set + * XXX NHM/WSM/SNB/IVB don't have the IFETCH bits set */ #define HSW_DMND_READ (HSW_DMND_DATA_RD|HSW_DMND_IFETCH| \ - HSW_PF_DATA_RD|HSW_PF_IFETCH| \ SNB_LLC_DATA_RD|SNB_LLC_IFETCH) - -/* XXX NHM/WSM/SNB/IVB dont have the PF bits set */ -#define HSW_DMND_WRITE (HSW_DMND_RFO|HSW_PF_RFO|SNB_LLC_RFO) - -#define HSW_DMND_PREFETCH (0) /* XXX broken ? */ +#define HSW_DMND_WRITE (HSW_DMND_RFO|SNB_LLC_RFO) +#define HSW_DMND_PREFETCH (HSW_PF_DATA_RD|HSW_PF_RFO|HSW_PF_IFETCH) #define HSW_DRAM_ANY (SNB_NO_SUPP|SNB_SNP_ANY|(0x78ULL << 23)) /* WTF */ @@ -570,8 +566,8 @@ static __initconst const u64 hsw_hw_cach [ C(RESULT_MISS) ] = HSW_DMND_WRITE|HSW_L3_MISS, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0x0, - [ C(RESULT_MISS) ] = 0x0, + [ C(RESULT_ACCESS) ] = HSW_DMND_PREFETCH|HSW_L3_ACCESS, + [ C(RESULT_MISS) ] = HSW_DMND_PREFETCH|HSW_L3_MISS, }, }, }; -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
