Hi all,
I am not very familiar with the interrupt subsystem, so sorry if this sounds a stupid question.
IIUC, when a interrupt happens on a SMP system and if there is no affinity set for it, it is delivered following a scheme decided by the interrupt controller.
For example, for the APIC, there is a round robin behaviour, so an interrupt will be raised on cpu0, then cpu1, and so on ...
Is there a way to know on which cpu a controller will raise the interrupt ? Thanks in advance -- Daniel -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
