On Fri, Feb 27, 2015 at 1:33 PM, Catalin Marinas <catalin.mari...@arm.com> wrote: > It's either badly formatted or I don't get it. Are the "stxr x1" and > "stxr x7" happening on the same CPU (P0)? If yes, that's badly written > code, not even architecturally compliant (you are not allowed other > memory accesses between ldxr and stxr).
OK. Is that the same case with ldaxr (acquire) and stlxr (release)? AFAIK, memory accesses between acquire and release exclusive operations are allowed. > >> The last store exclusive succeeds since the exclusive bit is set which >> should not happen. Clearing the exclusive bit before returning from cmpxchg >> prevents this happening. >> >> Now I am not sure how likely this will happen. One can argue that a cmpxchg() >> will not happen between an external ldxr/stxr. But isn't clearing the >> exclusive >> bit better? > > The only way cmpxchg() could happen between a different ldxr/stxr is > during an interrupt. But ERET automatically clears the exclusive > monitor, so the "stxr x7" would not succeed. That makes sense. But please consider the ldaxr/stlxr case and let me know. Thanks! -- Pranith -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/