On Fri, Feb 27, 2015 at 2:08 PM, Mark Rutland <[email protected]> wrote: > On Fri, Feb 27, 2015 at 06:44:19PM +0000, Pranith Kumar wrote: >> On Fri, Feb 27, 2015 at 1:33 PM, Catalin Marinas >> <[email protected]> wrote: >> > It's either badly formatted or I don't get it. Are the "stxr x1" and >> > "stxr x7" happening on the same CPU (P0)? If yes, that's badly written >> > code, not even architecturally compliant (you are not allowed other >> > memory accesses between ldxr and stxr). >> >> OK. Is that the same case with ldaxr (acquire) and stlxr (release)? >> AFAIK, memory accesses between acquire and release exclusive >> operations are allowed. > > The restriction on memory accesses in the middle of a load-exclusive > store-exclusive sequence applies to all the load/store-exclusive > variants, including ldaxr and stlxr. >
Thanks Mark. I am trying to see where this restriction is documented. Looking at: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/a64_data_transfer_alpha.html I do not see that mentioned. The only restriction relevant is that a stxr should use the same address as the most recent ldxr. Could you please point me to the relevant documentation? Thanks! -- Pranith -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
