On Mon, Mar 2, 2015 at 5:58 AM, Javier Martinez Canillas <[email protected]> wrote: > Hello Alan, > > On 03/02/2015 02:45 PM, One Thousand Gnomes wrote: >> On Fri, 27 Feb 2015 06:37:49 +0100 >> Javier Martinez Canillas <[email protected]> wrote: >> >>> The Low Pin Count bus was introduced by Intel and is only used >>> in x86 computers >> >> The LPC bus is in all but name a slightly chopped down ISA bus. It is not >> x86 specific any more, and indeed there are wishbone/LPC busses used on >> all sorts of systems and processor types. >> > > Thanks a lot for the clarification, I didn't know that. > >> The ChromeOS EC may well be X86 specific but if so please fix the commit >> message accordingly. >> > > I'll let the ChromiumOS folks to answer if EC connected through LPC will > only be used in x86 Chromebooks and non-x86 Chromebooks will always use > either SPI or I2C. Or if a non-x86 Chromebook with a EC connected through > LPC may exist in the future.
I doubt we'll connect it with LPC on anything but x86, on other platforms we tend to go with SPI or i2c instead. > To know if I should either update the commit message or drop $subject, > since after patch 1/3 the driver builds correctly in other architectures. I'll reword the commit message when I apply (which I'll do shortly). -Olof -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
